In recent years, for TFT substrates included in display devices such as a liquid crystal display device etc., a TFT including a semiconductor layer of an oxide semiconductor (hereinafter referred to as an oxide semiconductor layer), which has satisfactory characteristics (e.g., high mobility, high reliability, low off current, etc.), has been proposed as a switching element for each pixel, which is the smallest unit of an image, instead of conventional TFTs including a semiconductor layer of amorphous silicon (a-Si).
For example, a typical bottom-gate TFT includes a gate electrode provided on an insulating substrate such as a glass substrate etc., a gate insulating film covering the gate electrode, a semiconductor layer provided on the gate insulating film over the gate electrode, and a source electrode and a drain electrode provided on the gate insulating film, overlapping the semiconductor layer (the source and drain electrodes are separated from each other). A channel region is formed in a portion of the semiconductor layer which is exposed between the source and drain electrodes.
The source and drain electrodes have a predetermined thickness sufficient to reduce the electrical resistance in order to avoid or reduce a signal delay. A threshold voltage for driving the TFT depends on the thickness of the semiconductor layer. As the thickness of the semiconductor layer increases, a gate voltage for driving the TFT proportionately increases. Therefore, the semiconductor layer is formed to have as small a thickness as possible within a range which allows a desired threshold voltage for the TFT, so that the semiconductor layer is thinner than the source and drain electrodes. This structure is similar to that of the TFT including an oxide semiconductor layer.
In the TFT substrate, the TFT is covered by a protection insulating film, and a pixel electrode formed on the insulating film is connected to the drain electrode through a contact hole formed in the protection insulating film.
Such a TFT substrate including the bottom-gate TFT may be manufactured as follows, for example. A film to be etched is formed on an insulating substrate by sputtering, chemical vapor deposition (hereinafter referred to as CVD), etc. A photosensitive resin film is formed by an application technique on the film to be etched. The photosensitive resin film is exposed to light through a photomask and then developed to form a resist pattern. The film to be etched which has been exposed through the resist pattern is patterned by dry etching or wet etching. This series of steps is repeatedly performed.
Specifically, a commonly used method for manufacturing the TFT substrate including the bottom-gate TFT uses five photomasks. In this manufacturing method, for example, a first photomask is used to form the gate electrode on the glass substrate. After formation of the gate insulating film covering the gate electrode, a second photomask is used to form the oxide semiconductor layer. Next, a third photomask is used to form the source and drain electrodes. Next, the protection insulating film is formed to cover the source and drain electrodes. A fourth photomask is used to form the contact hole in the protection insulating film. Finally, a fifth photomask is used to form the pixel electrode.
For such a TFT substrate thus manufactured, the cost of preparing, maintaining, and managing as many as five photomasks is required, and in addition, it is necessary to perform a plurality of processes (application, exposure, development, etc.) on the photosensitive resin material during formation of each resist pattern using the corresponding photomask, i.e., a large number of manufacturing steps are required, resulting in a high manufacturing cost. Therefore, TFT structures which require a smaller number of photomasks in manufacture of the TFT substrate have been previously proposed.
For example, Patent Document 1 describes a top-gate TFT, which includes a source electrode and a drain electrode provided on an upper surface of a base substrate and separated from each other, an oxide semiconductor layer provided between the source and drain electrodes and covering side end portions facing each other of the source and drain electrodes, and a gate insulating film and a gate electrode successively formed on an upper surface of the oxide semiconductor layer, and that has a configuration in which the oxide semiconductor layer, the gate insulating film, and the gate electrode have the same contour pattern projected on the upper surface of the base substrate. Patent Document 1 also shows that the configuration makes it possible to form the TFT using two photomasks, i.e., a first photomask for forming the source and drain electrodes and a second photomask for forming the oxide semiconductor layer, the gate insulating film, and the gate electrode.